2k x 8 static ram cy7c128a cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 february 3, 2000 features ? automatic power-down when deselected cmos for optimum speed/power high speed ?15 ns low active power ? 660 mw (commercial) ? 688 mw (military?20 ns) low standby power ? 110 mw (20 ns) ttl-compatible inputs and outputs capable of withstanding greater than 2001v electrostat- ic discharge v ih of 2.2v functional description the cy7c128a is a high-performance cmos static ram or- ganized as 2048 words by 8 bits. easy memory expansion is provided by an active low chip enable (ce ), and active low output enable (oe ) and three-state drivers. the cy7c128a has an automatic power-down feature, reducing the power consumption by 83% when deselected. writing to the device is accomplished when the chip enable (ce ) and write enable (we ) inputs are both low. data on the eight i/o pins (i/o 0 through i/o 7 ) is written into the memory location specified on the address pins (a 0 through a 10 ). reading the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while write enable (we ) remains high. under these conditions, the contents of the memory location specified on the address pins will appear on the eight i/o pins. the i/o pins remain in high-impedance state when chip en- able (ce ) or output enable (oe ) is high or write enable (we ) is low. the cy7c128a utilizes a die coat to insure alpha immunity. logic block diagram pin configurations c128a?1 a 1 a 2 a 4 a 5 a 6 column decoder row decoder sense amps input buffer power down we oe i/o 0 ce i/o 1 i/o 2 i/o 3 top view lcc 1 2 3 4 5 6 7 8 9 10 11 14 15 16 20 19 18 17 21 24 23 22 top view dip/soj/soic 12 13 a 6 a 5 a 4 a 3 we v cc a 8 a 9 a 10 i/o 5 i/o 4 i/o 3 c128a?2 a 7 i/o 0 i/o 1 ce oe 128 x 16 x 8 array i/o 7 i/o 6 i/o 5 i/o 4 7c128a a 0 c128a?3 a 3 a 7 a 8 a 9 a 10 24 4 5 6 7 8 9 10 321 23 11 12 13 14 15 22 21 20 19 18 17 16 a 5 v cc 7c128a a 6 2 i/o a 4 a 3 a 2 a 1 we ce a 0 a 9 i/o 2 gnd i/o 7 i/o 6 a 2 a 1 a 0 3 i/o 4 i/o 5 i/o gnd a 7 a 8 oe a 10 i/o 7 i/o 6 i/o 0 i/o 1 selection guide 7c128a-15 7c128a-20 7c128a-25 7c128a-35 7c128a-45 maximum access time (ns) 15 20 25 35 45 maximum operating current (ma) commercial 120 120 120 120 120 military - 125 125 125 125 maximum standby current (ma) commercial 40 20 20 20 20 military - 20 20 20 20
cy7c128a 2 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied ............................................. ? 55 c to +125 c supply voltage to ground potential (pin 28 to pin 14) ........................................... ? 0.5v to +7.0v dc voltage applied to outputs in high z state ............................................... ? 0.5v to +7.0v dc input voltage ............................................ ? 3.0v to +7.0v output current into outputs (low) ............................. 20 ma static discharge voltage .......................................... >2001v (per mil-std-883, method 3015) latch-up current.................................................... >200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% military [1] ? 55 c to +125 c 5v 10% electrical characteristics over the operating range [2] 7c128a-15 7c128a-20 7c128a-25 7c128a-35,45 parameter description test conditions min. max. min. max. min. max. min. max. unit v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 0.4 v v ih input high voltage 2.2 v cc 2.2 v cc 2.2 v cc 2.2 v cc v v il input low voltage [3] ? 0.5 0.8 ? 0.5 0.8 ? 0.5 0.8 ? 0.5 0.8 v i ix input load current gnd < v i < v cc ? 10 +10 ? 10 +10 ? 10 +10 ? 10 +10 a i oz output leakage current gnd < v i < v cc output disabled ? 10 +10 ? 10 +10 ? 10 +10 ? 10 +10 a i os output short circuitcurrent [4] v cc = max., v out = gnd ? 300 ? 300 ? 300 ? 300 ma i cc v cc operating supply current v cc = max. i out = 0 ma com ? l 120 120 120 120 ma mil - 125 125 125 i sb1 automatic ce power-down current max. v cc , ce > v ih, min. duty cycle = 100% com ? l40 40 20 20ma mil - 40 40 20 i sb2 automatic ce power-down current max. v cc , ce 1 > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v com ? l40 20 20 20ma mil - 20 20 20 capacitance [5] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 10 pf c out output capacitance 10 pf notes: 1. t a is the ? instant on ? case temperature. 2. see the last page of this specification for group a subgroup testing information. 3. v il (min.) = ? 3.0v for pulse durations less than 30 ns. 4. not more than 1 output should be shorted at one time. duration of the short circuit should not exceed 30 seconds. 5. tested initially and after any design or process changes that may affect these parameters.
cy7c128a 3 ac test loads and waveforms 3.0v 5v output r1 481 ? r2 255 ? 30 pf including jig and scope gnd 90% 10% 90% 10% 5ns 5 ns 5v output c128a ? 4 r1 481 ? r2 255 ? 5pf including jig and scope c128a ? 5 (a) (b) output 1.73v equivalent to: th venin equivalent all input pulses 167 ? switching characteristics over the operating range [2, 6] 7c128a-15 7c128a-20 7c128a-25 7c128a-35 7c128a-45 parameter description min. max. min. max. min. max. min. max. min. max. unit read cycle t rc read cycle time 15 20 25 35 45 ns t aa address to data valid 15 20 25 35 45 ns t oha data hold from address change 5 5555ns t ace ce low to data valid 1520253545ns t doe oe low to data valid 1010121520ns t lzoe oe low to low z 33333ns t hzoe oe high to high z [7] 8 8 10 12 15 ns t lzce ce low to low z [8] 55555ns t hzce ce high to high z [7, 8] 8 8 10 15 15 ns t pu ce low to power-up 00000ns t pd ce high to power-down 1520202025ns write cycle [9] t wc write cycle time 15 20 20 25 40 ns t sce ce low to write end 1215202530ns t aw address set-up to write end1215202530ns t ha address hold from write end00000ns t sa address set-up to write start00000ns t pwe we pulse width 1215152020ns t sd data set-up to write end1010101515ns t hd data hold from write end00000ns t hzwe we low to high z [7] 7 7 7 10 15 ns t lzwe we high to low z 55555ns notes: 6. test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 7. t hzoe , t hzce , and t hzwe are specified with c l = 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady state voltage. 8. at any given temperature and voltage condition, t hzce is less than t lzce for any given device. 9. the internal write time of the memory is defined by the overlap of ce low and we low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input set-up and hold timing should be referenced to the rising edge of the signal that termina tes the write.
cy7c128a 4 switching waveforms read cycle no. 1 [10, 11] read cycle no. 2 [10, 12] write cycle no. 1 (we controlled) [9, ] notes: 10. we is high for read cycle. 11. device is continuously selected. oe , ce = v il . 12. address valid prior to or coincident with ce transition low. 13. data i/o pins enter high-impedance state, as shown, when oe is held low during write. address c128a ? 6 data o u t p r e v i o u s d a ta va l i d data valid t rc t aa t oha 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu data out high impedance impedance i cc i sb t hzoe t hzce t pd oe ce high c128a ? 7 v cc supply current t wc data undefined high impedance t sce t aw t sa t pwe t ha t hd t hzwe t lzwe t sd c128a ? 8 ce we data in data i/o address data in valid
cy7c128a 5 write cycle no. 2 (ce controlled) [9, 13, 14] notes: 14. if ce goes high simultaneously with we high, the output remains in a high-impedance state. switching waveforms (continued) t wc data undefined high impedance t sce t aw t sa t pwe t ha t hd t hzwe t sd address ce we data in data i/o c128a ? 9 data in val id typical dc and ac characteristics 1.2 1.4 1.0 0.6 0.4 0.2 4.0 4.5 5.0 5.5 6.0 1.6 1.4 1.2 1.0 0.8 ? 55 25 125 ? 55 25 125 1.2 1.0 0.8 normalized t aa 120 100 80 60 40 20 0.0 1.0 2.0 3.0 4.0 output source current (ma) supply voltage(v) normalized supply current vs. supply voltage normalized access time vs. ambient temperature ambient temperature( c) normalized supply current vs. ambient temperature ambient temperature( c) output voltage(v) output source current vs. output vo ltag e 0.0 0.8 1.4 1.3 1.2 1.1 1.0 0.9 4.0 4.5 5.0 5.5 6.0 normalized t aa supply voltage(v) normalized access time vs. supply voltage 120 140 100 60 40 20 0.0 1.0 2.0 3.0 4.0 output sink current (ma) 0 80 output voltage(v) output sink current vs. output voltage 0.6 0.4 0.2 0.0 normalized i cc , i sb normalized i cc , i sb i sb v cc = 5.0v v in = 5.0v i cc i cc v cc = 5.0v v cc =5.0v t a = 25 c v cc =5.0v t a = 2 5 c) i sb t a = 25 c 0.6 0.8 0
cy7c128a 6 typical dc and ac characteristics (continued) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.0 2.0 3.0 4.0 normalized i po supply voltage(v) typical power-on current vs. supply voltage 30.0 25.0 20.0 15.0 10.0 5.0 0 200 400 600 800 delta t (ns) aa capacitance (pf) typical access time change vs. output loading 1.4 1.2 1.0 10 20 30 40 normalized i cc cycle frequency (mhz) normalized i cc vs. cycle time 0.0 5.0 0.0 1000 0.8 v cc = 4.5v t a = 25 c 0 v cc = 5.0v t a = 25 c v in = 0.5v 0.9 1.1 1.3 ordering information speed (ns) ordering code package name package type operating range 15 cy7c128a-15pc p13 24-lead (300-mil) molded dip commercial cy7c128a-15vc v13 24-lead molded soj cy7c128a-15sc s13 24-lead (300-mil) molded soic 20 cy7c128a-20pc p13 24-lead (300-mil) molded dip commercial cy7c128a-20vc v13 24-lead molded soj cy7c128a-20sc s13 24-lead (300-mil) molded soic cy7c128a-20dmb d14 24-lead (300-mil) cerdip military cy7c128a-20lmb l53 24-pin rectangular leadless chip carrier 25 cy7c128a-25pc p13 24-lead (300-mil) molded dip commercial cy7c128a-25vc v13 24-lead molded soj cy7c128a-25sc s13 24-lead (300-mil) molded soic cy7c128a-25dmb d14 24-lead (300-mil) cerdip military 35 cy7c128a-35pc p13 24-lead (300-mil) molded dip commercial cy7c128a-35vc v13 24-lead molded soj cy7c128a-35sc s13 24-lead (300-mil) molded soic cy7c128a-35dmb d14 24-lead (300-mil) cerdip military 45 CY7C128A-45PC p13 24-lead (300-mil) molded dip commercial cy7c128a-45vc v13 24-lead molded soj cy7c128a-45sc s13 24-lead (300-mil) molded soic cy7c128a-45dmb d14 24-lead (300-mil) cerdip military cy7c128a-45lmb l53 24-pin rectangular leadless chip carrier
cy7c128a 7 military specifications group a subgroup testing document #: 38-00094-c dc characteristics parameter subgroups v oh 1, 2, 3 v ol 1, 2, 3 v ih 1, 2, 3 v il max. 1, 2, 3 i ix 1, 2, 3 i oz 1, 2, 3 i cc 1, 2, 3 i sb 1, 2, 3 switching characteristics parameter subgroups read cycle t rc 7, 8, 9, 10, 11 t aa 7, 8, 9, 10, 11 t oha 7, 8, 9, 10, 11 t ace 7, 8, 9, 10, 11 t doe 7, 8, 9, 10, 11 write cycle t wc 7, 8, 9, 10, 11 t sce 7, 8, 9, 10, 11 t aw 7, 8, 9, 10, 11 t ha 7, 8, 9, 10, 11 t sa 7, 8, 9, 10, 11 t pwe 7, 8, 9, 10, 11 t sd 7, 8, 9, 10, 11 t hd 7, 8, 9, 10, 11
cy7c128a 8 package diagrams 24-lead (300-mil) cerdip d14 mil-std-1835 d- 9 config.a 51-80031 24-pin rectangular leadless chip carrier l53 51-80066
cy7c128a ? cypress semiconductor corporation, 2000. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams (continued) 51-85013-a 24-lead (300-mil) molded dip p13/p13a 24-lead (300-mil) molded soj v13 51-85030-a
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